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CS5460A
6. PIN DESCRIPTIONS
Crystal Out
CPU Clock Output
Positive Digital Supply
Digital Ground
Serial Clock Input
Serial Data Output
Chip Select
Mode Select
Differential Voltage Input
Differential Voltage Input
Voltage Reference Output
Voltage Reference Input
XOUT
CPUCLK
VD+
DGND
SCLK
SDO
CS
MODE
VIN+
VIN-
VREFOUT
VREFIN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
XIN
SDI
EDIR
EOUT
INT
RESET
NC
PFMON
I IN+
I IN-
VA+
VA-
Crystal In
Serial Data Input
Energy Direction Indicator
Energy Output
Interrupt
Reset
No Connect
Power Fail Monitor
Differential Current Input
Differential Current Input
Positive Analog Supply
Analog Ground
Clock Generator
Crystal Out
Crystal In
CPU Clock Output
1,24
2
XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a
crystal to provide the system clock for the device. Alternatively, an external (CMOS
compatible clock) can be supplied into XIN pin to provide the system clock for the device.
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.
Control Pins and Serial Data I/O
Serial Clock Input
Serial Data Output
Chip Select
Mode Select
Interrupt
Energy Output
Energy Direction
Indicator
Serial Data Input
5
6
7
8
20
21
22
23
SCLK - A clock signal on this pin determines the input and output rate of the data for the
SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time
signals. The SCLK pin will recognize clocks only when CS is low.
SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance
state when CS is high.
CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO
pin to a high impedance state. CS should be changed when SCLK is low.
MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the
aid of an external serial EEPROM to receive commands and settings. When at logic low,
the CS5460A assumes normal “host mode” operation. This pin is pulled down to logic
low if left unconnected, by an internal pull-down resistor to DGND.
INT - When INT goes low it signals that an enabled event has occurred. INT is cleared
(logic 1) by writing the appropriate command to the CS5460A.
EOUT - The energy output pin output a fixed-width pulse rate output with a rate (pro-
grammable) proportional to real (billable) energy.
EDIR - The energy direction indicator indicates if the measured energy is negative.
SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK.
Measurement and Reference Input
Differential
Voltage Inputs
DS487F5
9,10
VIN+, VIN- - Differential analog input pins for voltage channel.
51
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